1. Field of the Invention
This invention relates generally to improved synchronous display pattern control circuitry which utilizes relatively simplified counter and respective decoder logic for the mechanization thereof.
2. Description of Prior Art
Integrated circuit electronic display modules such as those utilized, for example, in an electronic calculator or in a digital watch, generally require a coded counting sequence to drive particular segments comprising a decimal digit of the display at predetermined times. Frequently, a decade counter and a respective decoder circuit are employed for generating and for subsequently decoding the sequence. The counter usually counts in a well known monotonically increasing binary coded sequence from zero through nine. Hence, a coded counter logic and a corresponding decoded segment logic are developed. Implementation of the input terms for the conventional counter and the respective segment decoder logic is accomplished through a relatively large number of logic devices and relatively complex circuitry. The foregoing results in relatively slow operating speeds, increased space consumption and high costs of production of the display circuit.